Semiconductor devices are continuously improved to enhance device performance. As devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. For example, when gate to gate pitch is extremely scaled, the conventional source/drain contact formation leads to a significant issue with gate-to-source/drain shorts. It has been found that borderless contact formation prevents the gate from connecting to the source/drain and enables a greater process window.
To realize borderless contacts in replacement metal gate integration schemes, a dielectric cap may be used to isolate the gate from the source/drain contact. Typically, the process of forming the dielectric cap involves recessing work function metals in the gate, depositing a low resistivity metal fill material, and recessing the fill material before depositing the capping material. Uniformity in the thicknesses of the work function metals and the metal fill provide for uniform gate resistivity and improved performance. Therefore, improved recessing processes providing for uniform layer thicknesses would improve device performance.
Accordingly, it is desirable to provide integrated circuits with improved gate uniformity and methods for fabricating integrated circuits with improved gate uniformity. Also, it is desirable to provide integrated circuits and methods for fabricating integrated circuits which utilize recessing processes with improved control. Other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.